Digital signal processing device and digital signal processing method

ABSTRACT

An apparatus for processing a digital signal that generates a one-bit output signal using a delta-sigma modulation apparatus, which includes a quantizer for quantizing an integrated output of a sixth integrator to generate a one-bit output signal that is send to respective integrators through an adder under feedback processing to output the one-bit output signal to the outside of a six-order Delta-sigma modulator, and a control unit for generating a control signal that controls the feedback loop signal from the quantizer so as to change the signal level of a signal component of the audio frequency band of the one-bit output signal. The control unit receives an integrated output from a second integrator being an input side integrator of the six-order delta-sigma modulator.

This is a 371 of PCT/JP03/09614, filed Jul. 29, 2003.

TECHNICAL FIELD

The present invention relates to an apparatus and method for processinga digital signal, in particular, to an apparatus and method forprocessing a digital signal to generate a one-bit output signal using aΔΣ modulation apparatus.

This application claims priority of Japanese Patent Application No.2002-233575, filed on Aug. 9, 2002, the entirety of which isincorporated by reference herein.

BACKGROUND ART

The data format of a ΔΣ-modulated high speed one-bit audio signal is ofsignificantly high sampling frequency and of short data length, such assampling frequency of 64 times 44.1 kHz and data length of one bit, ascompared with that of a conventional digital audio signal, such assampling frequency of 44.1 kHz and data length of 16 bits, and ischaracterized by broad transmittable frequency band. Although theΔΣ-modulated signal is a one-bit signal, high dynamic range can besecured in audio frequency band which is low as compared with the oversampling frequency of 64 times. Taking advantage of the property, theΔΣ-modulated signal is applicable to data recording and datatransmission, keeping high sound quality.

A ΔΣ modulation circuit is not a particularly new technology, and isconventionally often used is an AD converter, etc. since it can beconfigured in the form of an IC properly and AD conversion with highaccuracy can be realized with ease relatively.

A ΔΣ-modulated signal can be restored to an analog audio signal bycausing the ΔΣ-modulated signal to pass through a simple analog low-passfilter.

In a ΔΣ-modulated signal, there exists the maximum amplitude level ofrepresentable audio frequency band. Thus, a large-level signal whoseamplitude level surpasses the maximum amplitude level cannot berepresented. Furthermore, when an overflowed signal, which is generatedby adding two kinds of one-bit signals, is sent to a ΔΣ modulator ofhigh order so as to obtain a one-bit signal, a signal processing circuitbecomes unstable.

For example, when mixing one-bit signals, the amplitude level of aresultant output signal may surpass that of original signals, or surpassan amplitude level that can be represented by a one-bit signal. Whenconverting such a large-level signal to a one-bit signal using a digitalsignal processing apparatus provided with a ΔΣ modulator of high order,it is necessary to perform limit processing for the amplitude level ofaudio frequency band using a limiter so as to prevent instability of asignal processing circuit.

FIG. 10 shows an example of a block diagram of a conventional digitalsignal processing apparatus 100. When adding two kinds of high speedone-bit signals A and B, generated through noise shaping, using an adder101, the amplitude level of a resultant added output undesirablysurpasses the maximum amplitude level of representable audio frequencyband. So, the digital signal processing apparatus 100 performs limitprocessing for an audio frequency band signal being the added output.

Firstly, an FIR filter 102 detects audio frequency band. Secondly, anover level detector 103 detects an over level surpassing from areference level. Then, the over level detector 103 sets thus detectedover level to be of negative, and an adder 105 adds thus generatednegative over level to the added output sent from the adder 101 which isdelayed by a delay line 104. Thus, the over level of the audio frequencyband is subtracted from the audio frequency band signal by the adder105, suppressing the over level. Then, the audio frequency band signalwhich has its over level suppressed is sent to a ΔΣ modulator 106 to bea one-bit output signal.

The FIR filter 102, which has to remove quantization noise componentconcentrated at high range raised after undergoing noise shaping so asto detect signal component of audio frequency band, is a filter havingsteep attenuation property. The FIR filter 102 of steep attenuationproperty is undesirably enlarged in size since multipliers, etc. areused. Furthermore, in view of delay time brought about by thelarge-sized FIR filter 102, the delay line 104 has to set long delaytime.

DISCLOSURE OF THE INVENTION

Accordingly, the present invention has an object to overcome theabove-mentioned drawbacks of the prior art by providing a new apparatusand method for processing a digital signal.

The present invention has another object to provide an apparatus andmethod for processing a digital signal which enable limit processingunder small-sized hardware configuration in performing ΔΣ modulation.

The above object can be attained by providing an apparatus forprocessing a digital signal having plural “m” sets of integratorsconnected in series that performs “m”-order ΔΣ modulation for a one-bitinput signal processed under predetermined signal processing, including:

quantization means for quantizing an output sent from the lastintegrator of the “m” sets of integrators connected in series togenerate a one-bit signal;

control means for generating a control signal that controls theamplitude level of signal component of audio frequency band of a one-bitsignal sent from the quantization means, the one-bit signal being to besent to the plural integrators under feedback processing; and

amplitude change means for changing the amplitude level of signalcomponent of audio frequency band of a one-bit signal sent from thequantization means based on the control signal sent from the controlmeans.

The control means generates the control signal based on an output sentfrom one integrator of the plural integrators connected in series. Thecontrol means has filter means for extracting signal component of audiofrequency band out of an output sent from one integrator of the pluralintegrators connected in series.

The control means compares an output sent from one integrator of theplural integrators connected in series with a predetermined referencesignal, and generates the control signal based on the comparison result.The control means further has level change means for multiplying thecomparison result between an output sent from one integrator of theplural integrators connected in series and a predetermined referencesignal by predetermined times. The control means may further havelimiter property change means for giving nonlinear property to thecomparison result between an output sent from one integrator of theplural integrators connected in series and a predetermined referencesignal.

The control means, which generates the control signal based on an outputsent from one integrator of the plural integrators connected in series,has

envelope peak detection means for detecting a peak of envelope from anoutput sent from one integrator of the plural integrators connected inseries over long time constant, and

over level ratio detection means for calculating a ratio of a peak valuedetected by the envelope peak detection means to a reference level, whenthe peak value surpasses the reference level, and generates the controlsignal based on thus calculated ratio.

The amplitude change means of the apparatus for processing a digitalsignal according to the present invention adds the control signal sentfrom the control means to a one-bit signal sent from the quantizationmeans to change the amplitude of a one-bit signal sent from thequantization means.

The amplitude change means may multiply a one-bit signal sent from thequantization means by the control signal sent from the control means tochange the amplitude of a one-bit signal sent from the quantizationmeans.

Also, the above object can be attained by providing a method forprocessing a digital signal using plural “m” sets of integratorsconnected in series that performs “m”-order ΔΣ modulation for a one-bitinput signal processed under predetermined signal processing, including:

quantization step of quantizing an output sent from the last integratorof the “m” sets of integrators connected in series to generate a one-bitsignal;

control step of generating a control signal that controls the amplitudelevel of signal component of audio frequency band of a one-bit signalthat is generated by quantizing an output of the last integrator, theone-bit signal being to be sent to the plural integrators under feedbackprocessing; and

amplitude change step of changing the amplitude level of signalcomponent of audio frequency band of a one-bit signal that is generatedby quantizing an output of the last integrator based on the controlsignal.

These objects and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription of the preferred embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of the first embodiment of an apparatus forprocessing a digital signal according to the present invention.

FIG. 2 shows a circuit diagram of a moving average filter.

FIG. 3 shows a circuit diagram of an over level detector.

FIG. 4A to FIG. 4F show timing charts for explaining the operation ofthe first embodiment of the digital signal processing apparatusaccording to the present invention.

FIG. 5 shows a block diagram of the second embodiment of an apparatusfor processing a digital signal according to the present invention.

FIG. 6 shows change property of a limiter property changer.

FIG. 7 shows a waveform of signal component of audio frequency band ofan output signal sent from the second embodiment of the digital signalprocessing apparatus according to the present invention.

FIG. 8A to FIG. 8G show timing charts for explaining the operation ofthe second embodiment of the digital signal processing apparatusaccording to the present invention.

FIG. 9 shows a block diagram of the third embodiment of an apparatus forprocessing a digital signal according to the present invention.

FIG. 10 shows a block diagram of a conventional digital signalprocessing apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

The apparatus and method for processing a digital signal of the presentinvention will further be described below concerning the best modes forcarrying out the present invention with reference to the accompanyingdrawings.

Referring to FIG. 1 to FIG. 4, the first embodiment of the presentinvention will be explained. FIG. 1 shows a block diagram of a digitalsignal processing apparatus 1 of the first embodiment which adds aone-bit signal A and a one-bit signal B, generated through ΔΣ modulationprocessing, using an adder 2, and sends a resulting added output to a ΔΣmodulator 3 of six order so as to output a one-bit signal.

The added output from the adder 2 sometimes surpasses the maximumamplitude level of audio frequency band which can be represented by aΔΣ-modulated one-bit signal due to overflow. Thus, a large-level signalsurpassing the maximum amplitude level of audio frequency band cannot berepresented by a one-bit signal.

When ΔΣ modulating the added output, the digital signal processingapparatus 1 sets a large-level signal surpassing the maximum amplitudelevel of audio frequency band to be of level which can be represented bya one-bit signal. In this processing, the digital signal processingapparatus 1 performs limit processing for the amplitude level of audiofrequency band of the added output so that its signal processing circuitdoes not become unstable, and outputs a one-bit signal.

So, the digital signal processing apparatus 1 includes a quantizer 33for quantizing an output of an integrator 30, which is the lastintegrator among six integrators of the six-order ΔΣ modulator 3, togenerate a one-bit output signal, and a control unit 4 for generating acontrol signal which controls a feedback loop signal to be sent torespective integrators among the one-bit output signal so as to changethe level of signal component of audio frequency band of the one-itoutput signal generated by the quantizer 33.

The six-order ΔΣ modulator 3 includes a first integrator 10, a secondintegrator 14, a third integrator 18, a fourth integrator 22, a fifthintegrator 26, and the sixth integrator 30. Moreover, the six-order ΔΣmodulator 3 includes a first coefficient multiplier 13 for multiplyingan integrated output from the first integrator 10 by a first coefficientto attenuate the integrated output, a second coefficient multiplier 17for multiplying an integrated output from the second integrator 14 by asecond coefficient to attenuate the integrated output, a thirdcoefficient multiplier 21 for multiplying an integrated output from thethird integrator 18 by a third coefficient to attenuate the integratedoutput, a fourth coefficient multiplier 25 for multiplying an integratedoutput from the fourth integrator 22 by a fourth coefficient toattenuate the integrated output, and a fifth coefficient multiplier 29for multiplying an integrated output from the fifth integrator 26 by afifth coefficient to attenuate the integrated output. Furthermore, thesix-order ΔΣ modulator 3 includes the quantizer 33 for quantizing anintegrated output from the sixth integrator 30 being the lastintegrator, and an adder 34 for adding the control signal generated bythe control unit 4 to the feedback loop signal from the quantizer 33 tobe sent to the respective integrators.

The first integrator 10 consists of an adder 11 and a shift arithmeticalelement 12. The second integrator 14 consists of an adder 15 and a shiftarithmetical element 16. The third integrator 18 consists of an adder 19and a shift arithmetical element 20. The fourth integrator 22 consistsof an adder 23 and a shift arithmetical element 24. The fifth integrator26 consists of an adder 27 and a shift arithmetical element 28. Thesixth integrator 30 consists of an adder 31 and a shift arithmeticalelement 32.

When an added output from the adder 2 is sent to the ΔΣ modulator 3, thefirst integrator 10 sends the added output to the shift arithmeticalelement 12 through the adder 11. The shift arithmetical element 12shifts an added output sent from the adder 11, and returns thus shiftedadded output to the adder 11. The adder 11 has the feedback loop signal,to which the control signal is added by the adder 34, sent thereto undernegative feedback. An integrated output of the first integrator 10 issent to the first coefficient multiplier 13. The first coefficientmultiplier 13 multiplies the integrated output from the first integrator10 by a first coefficient “ 1/32” to attenuate the integrated output,and sends thus attenuated integrated output to the second integrator 14.

The second integrator 14 sends a multiplied output from the firstcoefficient multiplier 13 to the shift arithmetical element 16 throughthe adder 15. The shift arithmetical element 16 shifts an added outputsent from the adder 15, and returns thus shifted added output to theadder 15. The adder 15 has the feedback loop signal, to which thecontrol signal is added by the adder 34, sent thereto under negativefeedback. An integrated output of the second integrator 14 is sent tothe second coefficient multiplier 17. The second coefficient multiplier17 multiplies the integrated output from the second integrator 14 by asecond coefficient “ 1/16” to attenuate the integrated output, and sendsthus attenuated integrated output to the third integrator 18.

The third integrator 18 sends a multiplied output from the secondcoefficient multiplier 17 to the shift arithmetical element 20 throughthe adder 19. The shift arithmetical element 20 shifts an added outputsent from the adder 19, and returns thus shifted added output to theadder 19. The adder 19 has the feedback loop signal, to which thecontrol signal is added by the adder 34, sent thereto under negativefeedback. An integrated output of the third integrator 18 is sent to thethird coefficient multiplier 21. The third coefficient multiplier 21multiplies the integrated output from the third integrator 18 by a thirdcoefficient “⅛” to attenuate the integrated output, and sends thusattenuated integrated output to the fourth integrator 22.

The fourth integrator 22 sends a multiplied output from the thirdcoefficient multiplier 21 to the shift arithmetical element 24 throughthe adder 23. The shift arithmetical element 24 shifts an added outputsent from the adder 23, and returns thus shifted added output to theadder 23. The adder 23 has the feedback loop signal, to which thecontrol signal is added by the adder 34, sent thereto under negativefeedback. An integrated output of the fourth integrator 22 is sent tothe fourth coefficient multiplier 25. The fourth coefficient multiplier25 multiplies the integrated output from the fourth integrator 22 by afourth coefficient “¼” to attenuate the integrated output, and sendsthus attenuated integrated output to the fifth integrator 26.

The fifth integrator 26 sends a multiplied output from the fourthcoefficient multiplier 25 to the shift arithmetical element 28 throughthe adder 27. The shift arithmetical element 28 shifts an added outputsent from the adder 27, and returns thus shifted added output to theadder 27. The adder 27 has the feedback loop signal, to which thecontrol signal is added by the adder 34, sent thereto under negativefeedback. An integrated output of the fifth integrator 26 is sent to thefifth coefficient multiplier 29. The fifth coefficient multiplier 29multiplies the integrated output from the fifth integrator 26 by a fifthcoefficient “½” to attenuate the integrated output, and sends thusattenuated integrated output to the sixth integrator 30.

The sixth integrator 30 sends a multiplied output from the fifthcoefficient multiplier 29 to the shift arithmetical element 32 throughthe adder 31. The shift arithmetical element 32 shifts an added outputsent from the adder 31, and returns thus shifted added output to theadder 31. The adder 31 has the feedback loop signal, to which thecontrol signal is added by the adder 34, sent thereto under negativefeedback. An integrated output of the sixth integrator 30 is sent to thequantizer 33.

The quantizer 33 quantizes the integrated output from the sixthintegrator 30 to output a one-bit signal. The one-bit signal is sent tothe respective integrators as the feedback loop signal under negativefeedback through the adder 34. The quantizer 33 outputs the one-bitoutput signal to the outside of the six-order ΔΣ modulator 3.

The control unit 4 generates a control signal that controls the feedbackloop signal sent from the quantizer 33 so as to change the level ofsignal component of audio frequency band of the one-bit output signal.So, the control unit 4 receives an integrated output from the secondintegrator 14 being an input side integrator of the six-order ΔΣmodulator 3.

The control unit 4 includes a moving average filter 5 for detectingsignal component of audio frequency band of the integrated output sentfrom the second integrator 14, an over level detector 6 for detecting anover level of the audio frequency band signal detected by the movingaverage filter 5, and a level changer 7 for changing the signal level ofan over level detected by the over level detector 6.

The moving average filter 5 has shift arithmetical elements 51 ₁ to 51₁₆ connected in series, and detects signal component of audio frequencyband out of the integrated output sent from the second integrator 14 byadding shifted outputs from the respective shift arithmetical elements51 ₁ to 51 ₁₆ using an adder 52.

The output of the second integrator 14 has its high range componentattenuated due to the property of the ΔΣ modulator, and dominatingly hassignal component of audio frequency band, while having certain highrange quantized noise component raised by noise shaping. In order toattenuate the noise component, signal component of audio frequency bandis detected using the 16-tap moving average filter 5. A filter used inthe control unit 4 may be a moving average filter with the number oftaps set to be approximately that shown in FIG. 2, and no multiplier isrequired to be provided. That is, a filter which can be realized with asmall-sized hardware.

In the digital signal processing apparatus 1, it is necessary toequalize delay time brought about by the filter of the control unit 4with that brought about by the second integrator 14 to the quantizer 33of the ΔΣ modulator 3. In this configuration, since delay time in thelatter case becomes of 16 samples, delay time in the control unit 4 canbe equalized with that brought about by the second integrator 14 to thequantizer 33 by using the moving average filter 5 of 16 taps.

The over level detector 6 compares signal component of audio frequencyband detected by the moving average filter 5 with a predeterminedreference level Lref to detect an over level. As shown in FIG. 3, signalcomponent of audio frequency band detected by the moving average filter5 is compared with the reference level Lref by a comparator 61, and thedifference therebetween is obtained by a subtractor 62. A changeoverterminal “a” of a changeover switch 63 receives an output of thesubtractor 62, while a changeover terminal “b” of the changeover switch63 is connected to the ground. A changeover segment “c” of thechangeover switch 63 is connected to the level changer 7. Thus, asubtracted level generated by the subtractor 62 can be output as an overlevel by controlling the changeover operation of the changeover switch63 based on the comparison result of the comparator 61. Specifically,when the comparator 61 judges that signal component of audio frequencyband surpasses the reference level Lref, the subtractor 62 detects asurpassing level to make it an over level and send the over level to thelevel changer 7 through the changeover switch 63.

The level changer 7 attenuates an audio frequency band signal sent fromthe second integrator 14 to one sixteenth so as to change the level ofthe audio frequency band signal from the second integrator 14 to a levelthat adapts to the level of an audio frequency band signal output fromthe ΔΣ modulator 3.

Thus, the control unit 4 changes the level of the over level of signalcomponent of audio frequency band, and sends thus level-changed overlevel to the adder 34. The adder 34 adds the level-changed over level toa quantized output from the quantizer 33. An added output from thesecond integrator 14 is sent to the respective integrators underfeedback processing. In this way, the control unit 4 generates a controlsignal to control the feedback loop signal sent from the quantizer 33 soas to change the level of signal component of audio frequency band. Inresult, the audio frequency band signal sent from the ΔΣ modulator 3becomes a signal that undergoes hard limit processing.

FIG. 4A to FIG. 4F show timing charts for explaining the operation ofthe digital signal processing apparatus 1.

FIG. 4A shows an output of the second integrator 14. The output of thesecond integrator 14 has its high range component attenuated due to theproperty of the ΔΣ modulator, and dominatingly has signal component ofaudio frequency band, while having certain high range quantized noisecomponent raised by noise shaping. In FIG. 4A, the output is shown by abold sinusoidal wave, which indicates that the signal waveform has highrange component.

FIG. 4B shows an output of the moving average filter 5. In FIG. 4B,signal component of audio frequency band which has its high rangecomponent removed is detected.

FIG. 4C shows over level component detected by the over level detector6. In detecting the over level component, ±8 along the ordinate axisshown in FIG. 4B is set to be the reference level Lref.

FIG. 4D shows a level-changed signal whose over level component isattenuated to one sixteenth so as to change the level of the audiofrequency band signal of the second integrator 14 to that of the audiofrequency band signal output from the ΔΣ modulator. The level-changedsignal corresponds to the control signal generated by the control unit4.

FIG. 4E is a signal that is generated at the adder 34 by adding thelevel-changed signal shown in FIG. 4D to the quantized output sent fromthe quantizer 33, that is, the feedback loop signal that is generated byadding the control signal to the quantized output.

FIG. 4F is signal component of audio frequency band of the one-bitoutput signal sent from the ΔΣ modulator 3. As shown in FIG. 4F, asignal waveform after passing through an analog low-pass filter isshown. The signal is caused to be a signal that undergoes hard limitprocessing.

As in the above, in the digital signal processing apparatus 1, themoving average filter 5, which brings about delay time equal to thatbrought about by the second integrator 14 to the quantizer 33 of the ΔΣmodulator 3, detects an audio frequency band signal, and detects overlevel component surpassing a reference level Lref. Then, after the levelof the over level component is changed, the resulting signal is added toa quantized output signal to generate a feedback loop signal, and thusgenerated feedback loop signal is sent to the respective integratorsunder feedback processing. Thus, limit processing for a ΔΣ-modulatedsignal can be realized using small-sized simple hardware configuration.

Next, referring to FIG. 5 to FIG. 8, the second embodiment of thepresent invention will be explained. FIG. 5 shows a block diagram of adigital signal processing apparatus 70 of the second embodiment whichadds a one-bit signal A and a one-bit signal B, generated through ΔΣmodulation processing, using an adder 2, and sends a resulting addedoutput to a ΔΣ modulator 3 of six order so as to output a one-bitsignal. In the digital signal processing apparatus 70 shown in FIG. 5,parts or components similar to those of the digital signal processingapparatus 1 shown in FIG. 1 are indicated with the same referencenumerals, and detailed explanation of which will be omitted.

The digital signal processing apparatus 70 includes a control unit 71whose configuration is different from that of the control unit 4 of thefirst embodiment. That is, the control unit 71 includes a moving averagefilter 5, an over level detector 6, a level changer 7, and furthermore,a limiter property changer 72 arranged at the downstream of the levelchanger 7.

The limiter property changer 72 performs limiter property changeprocessing for over level component whose level is changed by the levelchanger 7. FIG. 6 shows an example of change property for the limiterproperty change processing. In FIG. 6, the abscissa axis indicatesinput, while the ordinate axis indicates limit output. When inputs are0.125, 0.25, 0.375, then outputs are limited under non-linear propertyto be approximately 0.0208, 0.125, 0.25, respectively.

FIG. 7 shows a waveform of signal component of audio frequency band of aone-bit output signal generated based on a control signal that undergoesthe limiter property change processing at the limiter property changer72. The waveform is obtained by causing a one-bit output signal sentfrom the digital signal processing apparatus 70 to pass through ananalog low-pass filter.

FIG. 8A to FIG. 8G show timing charts for explaining the operation ofthe digital signal processing apparatus 70. Timing charts shown in FIG.8A to FIG. 8D are similar to those shown in FIG. 4A to FIG. 4D. FIG. 8Ashows an output of the second integrator 14, FIG. 8B shows an output ofthe moving average filter 5, FIG. 8C shows over level component detectedby the over level detector 6, and FIG. 8D shows a level-changed signalwhose over level component is attenuated to one sixteenth so as tochange the level of the audio frequency band signal of the secondintegrator 14 to that of the audio frequency band signal output from theΔΣ modulator.

FIG. 8E shows a limiter property change signal sent from the limiterproperty changer 72. In FIG. 8E, parts corresponding to respective peaksof the level-changed signal shown in FIG. 8D are caused to be gradual.The limiter property change signal corresponds to a control signalgenerated by the control unit 71.

FIG. 8F is a feedback loop signal that is generated at the adder 34 byadding the limiter property change signal (control signal) shown in FIG.8E to the quantized output sent from the quantizer 33.

FIG. 8G is signal component of audio frequency band of the one-bitoutput signal sent from the ΔΣ modulator 3. The waveform of the signalcomponent is similar to that of the signal component shown in FIG. 7.The signal is caused to be a signal that undergoes soft limitprocessing.

As in the above, in the digital signal processing apparatus 70, themoving average filter 5, which brings about delay time equal to thatbrought about by the second integrator 14 to the quantizer 33 of the ΔΣmodulator 3, detects an audio frequency band signal, and detects overlevel component surpassing a reference level Lref. Then, after the levelof the over level component is changed and thus level-changed signalundergoes the limiter property change processing, the resulting signalis added to a quantized output signal to generate a feedback loopsignal, and thus generated feedback loop signal is sent to therespective integrators under feedback processing. Thus, soft limitproperty for a ΔΣ-modulated signal can be realized using small-sizedsimple hardware configuration.

Next, referring to FIG. 9, the third embodiment of the present inventionwill be explained. FIG. 9 shows a block diagram of a digital signalprocessing apparatus 80 of the third embodiment which adds a one-bitsignal A and a one-bit signal B, generated through ΔΣ modulationprocessing, using an adder 2, and sends a resulting added output to a ΔΣmodulator 81 of six order so as to output a one-bit signal. In thedigital signal processing apparatus 80, a part of internal configurationof the six-order ΔΣ modulator 81 and a part of internal configuration ofa control unit 83 are different from those of the first embodiment. Inthe digital signal processing apparatus 80 shown in FIG. 9, parts orcomponents similar to those of the digital signal processing apparatus 1shown in FIG. 1 are indicated with the same reference numerals, anddetailed explanation of which will be omitted.

The six-order ΔΣ modulator 81 includes a multiplier 82 instead of theadder 34 used in the first embodiment. The multiplier 82 multiplies aquantized one-bit signal sent from the quantizer 33, to be sent to therespective integrators under feedback processing, by a control signalgenerated by the control unit 83.

The control unit 83 includes a moving average filter 5, and furthermore,an envelope peak detector 84 and an over level ratio detector 85 botharranged at the downstream of the moving average filter 5. The overlevel ratio detector 85 detects an over level ratio, and the controlunit 83 sends thus detected over level ratio to the multiplier 82 as acontrol signal. The multiplier 82 multiplies the quantized output sentfrom the quantizer 33 by the over level ratio.

The envelope peak detector 84 detects the peak level of envelope out ofthe audio frequency band signal detected by the moving average filter 5over long time constant. The over level ratio detector 85 calculates aratio or proportion of the peak level detected by the envelope peakdetector 84 to a reference level, when the peak level surpasses thereference level, and sets the ratio to be an over level ratio. Forexample, when a peak value of ±9.6 is detected in the output of themoving average filter 5 shown in FIG. 4B, the over level ratio of thepeak value to the reference level Lref of ±8 is 1.2. The control unit 83sends thus calculated over level ratio of 1.2 to the multiplier 82.Then, the multiplier 82 multiplies the quantized output sent from thequantizer 33 by the over level ratio of 1.2. Thus, automatic gaincontrol (AGC) can be realized.

As in the above, in the digital signal processing apparatus 80, themoving average filter 5, which brings about delay time equal to thatbrought about by the second integrator 14 to the quantizer 33 of the ΔΣmodulator 81, detects an audio frequency band signal, and detects anover level ratio surpassing a reference level. Then, after multiplying aquantized output signal by the over level ratio to perform AGC togenerate a feedback loop signal, thus generated feedback loop signal issent to the respective integrators under feedback processing. Thus,limit property for a ΔΣ-modulated signal can be realized usingsmall-sized simple hardware configuration.

In the first to third embodiment, the six-order ΔΣ modulator is used,and signal component of audio frequency band is detected from the secondintegrator. On the other hand, the present invention is not restrictedto above-described configurations, and other configurations may beemployed so long as processing time by the moving average filter isequalized with delay time brought about by the ΔΣ modulator.

For example, a five-order ΔΣ modulator may be used to detect signalcomponent of audio frequency band from a second integrator so as toperform limit processing in the same way as the first to thirdembodiments. In this case, a moving average filter of 8 taps is used.

Moreover, a four-order ΔΣ modulator may be used to detect signalcomponent of audio frequency band from a second integrator. In thiscase, a moving average filter of 4 taps is used. In case signalcomponent of audio frequency band is detected from a first integrator, amoving average filter of 8 taps is used.

Furthermore, a three-order ΔΣ modulator may be used to detect signalcomponent of audio frequency band from a second integrator. In thiscase, a moving average filter of 2 taps is used.

Yet furthermore, a seven-order ΔΣ modulator may be used to detect signalcomponent of audio frequency band from a second integrator. In thiscase, a moving average filter of 32 taps is used. Also, a seven-order ΔΣmodulator may be used to detect signal component of audio frequency bandfrom a third integrator using a moving average filter of 16 taps.

Yet furthermore, an eight-order ΔΣ modulator may be used to detectsignal component of audio frequency band from a second integrator. Inthis case, a moving average filter of 64 taps is used. Also, aseven-order ΔΣ modulator may be used to detect signal component of audiofrequency band from a third integrator using a moving average filter of32 taps. Also, a seven-order ΔΣ modulator may be used to detect signalcomponent of audio frequency band from a fourth integrator using amoving average filter of 16 taps.

In these examples, after signal component of audio frequency band isdetected using a moving average filter, a control signal is generated inthe same way as the first to third embodiments.

In the first to third embodiments, as an example in which the level ofsignal component of audio frequency band is enlarged, the case of addingor mixing two one-bit signals is explained. On the other hand, thepresent invention can be applied to various cases in which the signallevel of a processed signal surpasses those of original signals, forexample, mixing signals of multiple channels such as three, four, five,six channels, or level controlling of fade-in, fade-out, cross fade.

While the invention has been described in accordance with certainpreferred embodiments thereof illustrated in the accompanying drawingsand described in the above description in detail, it should beunderstood by those ordinarily skilled in the art that the invention isnot limited to the embodiments, but various modifications, alternativeconstructions or equivalents can be implemented without departing fromthe scope and spirit of the present invention as set forth and definedby the appended claims.

Industrial Applicability

According to the apparatus and method for processing a digital signal ofthe present invention, a filter such as a moving average filter withdelay time equal to that brought about by an input side integrator to aquantizer of a ΔΣ modulator detects an audio frequency band signal, anda control signal is generated based on a over level surpassing areference level, and the control signal is added to a quantized outputsignal or a quantized output signal is multiplied by the control signalto generate a feedback loop signal. Then, thus generated feedback loopsignal is sent to the respective integrators under feedback processing.Thus, limit processing for a ΔΣ-modulated signal can be realized undersimple configuration.

1. An apparatus for processing a digital signal having a plurality ofintegrators connected in series that perform modulation for a one-bitinput signal, comprising: quantization means for quantizing an outputsent from the last integrator of the plurality of integrators connectedin series to generate a one-bit signal; control means for generating acontrol signal that controls an amplitude level of a signal component ofan audio frequency band of a one-bit signal sent from the quantizationmeans, the one-bit signal being sent to the plurality of integratorsunder feedback processing; and amplitude change means for changing anamplitude level of a signal component of an audio frequency band of aone-bit signal sent from the quantization means based on the controlsignal sent from the control means, wherein the control means generatesthe control signal based on an output sent from one integrator of theplurality of integrators connected in series.
 2. The apparatus forprocessing a digital signal as set forth in claim 1, wherein the controlmeans comprises filter means for extracting the signal component of theaudio frequency band out of an output sent from one integrator of theplurality of integrators connected in series.
 3. The apparatus forprocessing a digital signal as set forth in claim 2, wherein the filtermeans generates a time delay to adjust a time delay brought about by theplurality of integrators.
 4. The apparatus for processing a digitalsignal as set forth in claim 1, wherein the control means comprisesmeans for comparing an output sent from the one integrator of theplurality of integrators connected in series with a predeterminedreference signal and generates the control signal based on a result ofthe comparison.
 5. The apparatus for processing a digital signal as setforth in claim 4, wherein the control means further comprises levelchange means for multiplying the result of the comparison between theoutput sent from the one integrator of the plurality of integratorsconnected in series and the predetermined reference signal apredetermined number of times.
 6. The apparatus for processing a digitalsignal as set forth in claim 5, wherein the control means further haslimiter property change means for giving a non-linear property to theresult of the comparison between the output sent from the one integratorof the plurality of integrators connected in series and thepredetermined reference signal.
 7. The apparatus for processing adigital signal as set forth in claim 1, wherein the control meanscomprises: envelope peak detection means for detecting a peak of anenvelope of an output sent from the one integrator of the plurality ofintegrators connected in series over a long time constant, and overlevel ratio detection means for calculating a ratio of a peak valuedetected by the envelope peak detection means to a reference level whenthe peak value surpasses the reference level, and the control meansgenerates the control signal based on the calculated ratio.
 8. Theapparatus for processing a digital signal as set forth in claim 1,wherein the amplitude change means adds the control signal sent from thecontrol means to a one-bit signal sent from the quantization means tochange the amplitude level of the one-bit signal sent from thequantization means.
 9. The apparatus for processing a digital signal asset forth in claim 1, wherein the amplitude change means multiplies aone-bit signal sent from the quantization means by the control signalsent from the control means to change the amplitude level of the one-bitsignal sent from the quantization means.
 10. A method for processing adigital signal using a plurality of integrators connected in series thatperforms modulation for a one-bit input signal, comprising: aquantization step of quantizing an output sent from the last integratorof the plurality of integrators connected in series to generate aone-bit signal; a control step of generating a control signal thatcontrols an amplitude level of a signal component of an audio frequencyband of the one-bit signal that is generated by the quantization step,the one-bit signal being sent to the plurality of integrators underfeedback processing; and an amplitude change step of the changing theamplitude level of signal component of the audio frequency band of theone-bit signal that is generated by the quantization step based on thecontrol signal, wherein the control signal is generated based on anoutput sent from one integrator of the plurality of integratorsconnected in series.
 11. The method for processing a digital signal asset forth in claim 10, wherein in generating the control signal, thesignal component of the audio frequency band is extracted out of anoutput sent from the one integrator of the plurality of integratorsconnected in series using a filter.
 12. The method for processing adigital signal as set forth in claim 10, wherein the control signal isgenerated based on a comparison result obtained by comparing an outputsent from the one integrator of the plurality of integrators connectedin series with a predetermined reference signal.
 13. The method forprocessing a digital signal as set forth in claim 12, wherein ingenerating the control signal, a level change is further performed inwhich the comparison result between the output sent from the oneintegrator of the plurality of integrators connected in series and thepredetermined reference signal is multiplied a predetermined number oftimes.
 14. The method for processing a digital signal as set forth inclaim 13, wherein in generating the control signal, limiter propertychange is further performed in which a non-linear property is given tothe comparison result between the output sent from the one integrator ofthe plurality of integrators connected in series and the predeterminedreference signal.
 15. The method for processing a digital signal as setforth in claim 11, wherein in generating the control signal, a peakvalue of an envelope is detected from the output sent from the oneintegrator of the plurality of integrators connected in series over along time constant, and a ratio of the detected peak value to areference level, when the peak value surpasses the reference level, iscalculated, and the control signal is generated based on the calculatedratio.
 16. The method for processing a digital signal as set forth inclaim 10, wherein in changing the amplitude level, the control signal isadded to the one-bit signal that is generated by quantizing an output ofthe last integrator to change the amplitude level of the one-bit signalthat is generated by quantizing the output of the last integrator.